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| author | Nico Huber <nico.h@gmx.de> | 2017-09-01 22:48:07 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-09-05 08:27:51 +0000 |
| commit | 5bceca1c530cbb8412828a937085e9afc035e212 (patch) | |
| tree | 922bf7b37a6bc42c49f7a599c885a5faec85278c /src/soc/intel/cannonlake | |
| parent | 824c85c9a514aa32b508bffda8a18e834243085f (diff) | |
| download | coreboot-5bceca1c530cbb8412828a937085e9afc035e212.tar.xz | |
nb/intel/common: Write MRC cache at exit of BS_DEV_INIT
We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat-
forms now. The SPI controller is initialized at start of BS_DEV_INIT
(dev_initialize()).
The SPI lockdown usually shouldn't be a problem but the SPI driver imple-
mentation lacks full support for the locked interface. Also, some options
exist to lock all flash regions read-only until the next reboot.
Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
0 files changed, 0 insertions, 0 deletions