diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-01-08 13:57:43 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-01-09 09:55:23 +0000 |
| commit | b3585b9b351adbce05515581e13a6039f8cd4dd3 (patch) | |
| tree | 2176d644d103af1051867f652d1c2beb2925de58 /src/soc/intel/cannonlake | |
| parent | 567b4ee0b9abcbbc66cd912461f027953919b725 (diff) | |
| download | coreboot-b3585b9b351adbce05515581e13a6039f8cd4dd3.tar.xz | |
soc/intel/cannonlake: Remove redundent CNL CPUID macros
This patch ensures all CannonLake CPUIDs are part of mp_init.h
hence remove duplicate macro definitions from SoC code.
TEST=Build and boot CannonLake RVP
Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/report_platform.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/cpu.h | 8 |
2 files changed, 3 insertions, 9 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 9bca7acd23..969a8f73f9 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,8 +20,8 @@ #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/mp_init.h> #include <soc/bootblock.h> -#include <soc/cpu.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <string.h> diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index e50801f0b0..bde8f28f1a 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,12 +21,6 @@ #include <device/device.h> #include <intelblocks/msr.h> -/* Supported CPUIDs */ -#define CPUID_CANNONLAKE_A0 0x60660 -#define CPUID_CANNONLAKE_B0 0x60661 -#define CPUID_CANNONLAKE_C0 0x60662 -#define CPUID_CANNONLAKE_D0 0x60663 - /* Latency times in units of 1024ns. */ #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 |