diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-03-21 11:10:03 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-06 16:09:12 +0000 |
| commit | bf0970e762a6611cef06af761bc2dec068d439bb (patch) | |
| tree | 44d4854b7027794bc5a76b44a4e8fd07935cd60c /src/soc/intel/cannonlake | |
| parent | 161eafb0fb9563decbb953d5dccac4762b770e0c (diff) | |
| download | coreboot-bf0970e762a6611cef06af761bc2dec068d439bb.tar.xz | |
src: Use include <delay.h> when appropriate
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/lpc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 7c6025cb75..56fefa5c05 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#include "chip.h" -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <pc80/isa-dma.h> @@ -34,6 +32,8 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> +#include "chip.h" + /* * As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve * certain memory range as reserved range for BIOS usage. |