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authorFurquan Shaikh <furquan@chromium.org>2017-10-11 14:44:29 -0700
committerFurquan Shaikh <furquan@google.com>2017-10-12 22:13:39 +0000
commitc4e652ff572d7eea3bbbae21825d0085e294cb98 (patch)
tree7a9a5ad7d0374742bb7ac091dc4f2814795e47ad /src/soc/intel/cannonlake
parentbbd5ee4187dd5b85a8ccf6de28b24a70c0343174 (diff)
downloadcoreboot-c4e652ff572d7eea3bbbae21825d0085e294cb98.tar.xz
soc/intel/common: Clean up PMC library GPE handling API
1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/pmutil.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index cee3f95a10..ed2e3b0338 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -106,7 +106,7 @@ const char *const *soc_tco_sts_array(size_t *a)
* GPE0
*/
-const char *const *soc_gpe_sts_array(size_t *a)
+const char *const *soc_std_gpe_sts_array(size_t *a)
{
static const char *const gpe_sts_bits[] = {
[1] = "HOTPLUG",
@@ -174,7 +174,7 @@ uintptr_t soc_read_pmc_base(void)
return (uintptr_t)pmc_mmio_regs();
}
-void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
+void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{
DEVTREE_CONST struct soc_intel_cannonlake_config *config;