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authorFelix Singer <felix.singer@secunet.com>2020-08-04 16:47:10 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-08-07 20:35:29 +0000
commit3de90d134494203556a81c47a6640ae101674114 (patch)
tree85ec6d856aeba4da218ea3ae5038565eab6bbd89 /src/soc/intel/cannonlake
parentb7594b09b597075b3072e12c8338ca0cee66c006 (diff)
downloadcoreboot-3de90d134494203556a81c47a6640ae101674114.tar.xz
soc/intel/cnl: Set Heci1Disable depending on devicetree config
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0853cca488..0779ce2e44 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -525,7 +525,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Heci3Enabled = config->Heci3Enabled;
#if !CONFIG(HECI_DISABLE_USING_SMM)
- params->Heci1Disabled = !config->HeciEnabled;
+ dev = pcidev_path_on_root(PCH_DEVFN_CSE);
+ params->Heci1Disabled = !is_dev_enabled(dev);
#endif
params->Device4Enable = config->Device4Enable;