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authorDuncan Laurie <dlaurie@google.com>2019-01-23 14:55:47 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-01-25 11:22:06 +0000
commit52b5b587f1bc5d23d20959f1cae664038d6a42ea (patch)
tree4f4ec6c9d30ec51a825f945a4b6174509c56e88e /src/soc/intel/cannonlake
parent38e40414d250abfdc7213e6dfa11beb8d7082489 (diff)
downloadcoreboot-52b5b587f1bc5d23d20959f1cae664038d6a42ea.tar.xz
soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery
Disabling CpuRatio UPD for FSP will ensure it does not force a hard reset to set the CPU Flex Ratio at boot. This is important in a recovery mode boot where the SOC will lose power and need to set the flex ratio again. Disabling SaGv makes recovery mode training faster and mirrors the setting that was done on Skylake. BUG=b:123305400 TEST=reliably enter recovery mode on sarien Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 91810e8e6e..bdaa4afaf1 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -17,9 +17,11 @@
#include <chip.h>
#include <console/console.h>
#include <fsp/util.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
+#include <vendorcode/google/chromeos/chromeos.h>
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
{
@@ -54,6 +56,21 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
#endif
+
+ /* Disable CPU Flex Ratio and SaGv in recovery mode */
+ if (vboot_recovery_mode_enabled()) {
+ struct chipset_power_state *ps = pmc_get_power_state();
+
+ /*
+ * Only disable when coming from S5 (cold reset) otherwise
+ * the flex ratio may be locked and FSP will return an error.
+ */
+ if (ps && ps->prev_sleep_state == ACPI_S5) {
+ m_cfg->CpuRatio = 0;
+ m_cfg->SaGv = 0;
+ }
+ }
+
/* If ISH is enabled, enable ISH elements */
if (!dev)
m_cfg->PchIshEnable = 0;