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authorSubrata Banik <subrata.banik@intel.com>2018-05-17 18:40:32 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-01-10 12:18:34 +0000
commit7bc4dc5648c6ff37a847e99d7acee11e3e72a79d (patch)
treec7137be28a68c96d3711c77ef7bbd9d288d6569f /src/soc/intel/cannonlake
parente7184b0ad07b0d3fe3e2f58bacd5e10e3cd88a79 (diff)
downloadcoreboot-7bc4dc5648c6ff37a847e99d7acee11e3e72a79d.tar.xz
soc/intel/common/block: Move tco common functions into block/smbus
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c36
-rw-r--r--src/soc/intel/cannonlake/finalize.c9
-rw-r--r--src/soc/intel/cannonlake/include/soc/smbus.h13
-rw-r--r--src/soc/intel/cannonlake/pmutil.c33
-rw-r--r--src/soc/intel/cannonlake/romstage/power_state.c8
5 files changed, 13 insertions, 86 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 73e159ab09..f45e177c0a 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +24,7 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -52,8 +53,6 @@
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_TCOBASE 0x2778
-#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
@@ -141,35 +140,6 @@ static void soc_config_acpibase(void)
}
}
-static void soc_config_tco(void)
-{
- uint32_t reg32;
- uint16_t tcobase;
- uint16_t tcocnt;
-
- /* Disable TCO in SMBUS Device first before changing Base Address */
- reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
- reg32 &= ~TCO_BASE_EN;
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
-
- /* Program TCO Base */
- tcobase = TCO_BASE_ADDRESS;
- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase);
-
- /* Enable TCO in SMBUS */
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN);
-
- /*
- * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
- */
- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
-
- /* Program TCO timer halt */
- tcocnt = inw(tcobase + TCO1_CNT);
- tcocnt |= TCO_TMR_HLT;
- outw(tcocnt, tcobase + TCO1_CNT);
-}
-
static int pch_check_decode_enable(void)
{
uint32_t dmi_control;
@@ -216,7 +186,7 @@ void pch_early_init(void)
soc_config_acpibase();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
- soc_config_tco();
+ tco_configure();
/* Program SMBUS_BASE_ADDRESS and Enable it */
smbus_common_init();
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index b3c07b1154..03ff616a60 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
+#include <intelblocks/tco.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <soc/p2sb.h>
@@ -55,17 +56,11 @@ static void pch_finalize(void)
{
struct device *dev;
uint32_t reg32;
- uint16_t tcobase, tcocnt;
uint8_t *pmcbase;
config_t *config;
uint8_t reg8;
- /* TCO Lock down */
- tcobase = smbus_tco_regs();
- tcocnt = inw(tcobase + TCO1_CNT);
- tcocnt |= TCO_LOCK;
- outw(tcocnt, tcobase + TCO1_CNT);
-
+ tco_lockdown();
/*
* Disable ACPI PM timer based on dt policy
*
diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h
index 9f1cf34862..e3d93a2a54 100644
--- a/src/soc/intel/cannonlake/include/soc/smbus.h
+++ b/src/soc/intel/cannonlake/include/soc/smbus.h
@@ -4,7 +4,7 @@
* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,11 +19,6 @@
#ifndef _SOC_CANNONLAKE_SMBUS_H_
#define _SOC_CANNONLAKE_SMBUS_H_
-/* PCI registers */
-#define TCOBASE 0x50 /* TCO base address. */
-#define TCOCTL 0x54
-#define TCO_BASE_EN (1 << 8) /* TCO base enable. */
-
/* IO and MMIO registers under primary BAR */
/* Set address for PCH as SMBus slave role */
#define SMB_RCV_SLVA 0x09
@@ -32,10 +27,10 @@
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
-#define TCO2_STS_SECOND_TO (1 << 1)
+#define TCO_STS_SECOND_TO (1 << 1)
#define TCO1_CNT 0x08
-#define TCO_LOCK (1 << 12)
-#define TCO_TMR_HLT (1 << 11)
+#define TCO_LOCK (1 << 12)
+#define TCO_TMR_HLT (1 << 11)
/*
* Default slave address value for PCH. This value is set to match default
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 951d8863ac..b57102df42 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -29,6 +29,7 @@
#include <console/console.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
+#include <intelblocks/tco.h>
#include <halt.h>
#include <rules.h>
#include <stdlib.h>
@@ -154,38 +155,6 @@ uint8_t *pmc_mmio_regs(void)
return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
}
-uint16_t smbus_tco_regs(void)
-{
- uint16_t reg16;
-
- reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
-
- return ALIGN_DOWN(reg16, 0x20);
-}
-
-uint32_t soc_reset_tco_status(void)
-{
- u16 tco1_sts;
- u16 tco2_sts;
- u16 tcobase;
-
- tcobase = smbus_tco_regs();
-
- /* TCO Status 2 register */
- tco2_sts = inw(tcobase + TCO2_STS);
- tco2_sts |= TCO2_STS_SECOND_TO;
- outw(tco2_sts, tcobase + TCO2_STS);
-
- /* TCO Status 1 register */
- tco1_sts = inw(tcobase + TCO1_STS);
-
- /* Clear SECOND_TO_STS bit */
- if (tco2_sts & TCO2_STS_SECOND_TO)
- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
-
- return (tco2_sts << 16) | tco1_sts;
-}
-
uintptr_t soc_read_pmc_base(void)
{
return (uintptr_t)pmc_mmio_regs();
diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c
index 72361ff83a..99a93accbe 100644
--- a/src/soc/intel/cannonlake/romstage/power_state.c
+++ b/src/soc/intel/cannonlake/romstage/power_state.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/device.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/tco.h>
#include <string.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -66,13 +67,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
void soc_fill_power_state(struct chipset_power_state *ps)
{
- uint16_t tcobase;
uint8_t *pmc;
- tcobase = smbus_tco_regs();
-
- ps->tco1_sts = inw(tcobase + TCO1_STS);
- ps->tco2_sts = inw(tcobase + TCO2_STS);
+ ps->tco1_sts = tco_read_reg(TCO1_STS);
+ ps->tco2_sts = tco_read_reg(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
ps->tco1_sts, ps->tco2_sts);