diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-02 18:28:22 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 17:32:37 +0000 |
| commit | a1843d8411d3caebd0600421c2b6a4c6b0588c19 (patch) | |
| tree | d1baeb97ea1ca28ca09df0ceb3edd53ef0eea029 /src/soc/intel/cannonlake | |
| parent | 8a64ad09a100adf478d65e42e4cc10a18ccc2d16 (diff) | |
| download | coreboot-a1843d8411d3caebd0600421c2b6a4c6b0588c19.tar.xz | |
soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.
Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.
Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 5 |
3 files changed, 3 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d61435aaa6..7b9b88be61 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select REG_SCRIPT + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index dc24e9bd8f..2a52627be7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -273,8 +273,6 @@ struct soc_intel_cannonlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SLP_S3 Minimum Assertion Width Policy * 1 = 60us diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index fe7641f27b..9b28d3d795 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -248,6 +248,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; @@ -432,9 +434,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; - /* Disable PCH ACPI timer */ - params->EnableTcoTimer = !config->PmTimerDisabled; - /* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert) params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; |