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authorSridhar Siricilla <sridhar.siricilla@intel.com>2020-08-05 16:16:52 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-08-12 17:39:49 +0000
commita91c9196116af77a7d4c9d4a56c7b514fa961d76 (patch)
treed1510f3466bc3905ecdb89d3e1999934a31c07ea /src/soc/intel/cannonlake
parent4dfdce4223e9689d230809b64178af4af60b0dd6 (diff)
downloadcoreboot-a91c9196116af77a7d4c9d4a56c7b514fa961d76.tar.xz
soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR address is overridden with 0xfed1a000. This causes HECI transactions to fail between FSP-M call and postcar. BRANCH=puff TEST=Verified sending HECI commands before and after FSP-M call on hatch. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 37f4d50b0b..ac42e0054a 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -157,6 +157,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* Configure VT-d */
tconfig->VtdDisable = 0;
+ /* Set HECI1 PCI BAR address */
+ m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;
+
mainboard_memory_init_params(mupd);
}