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authorFurquan Shaikh <furquan@google.com>2019-02-27 00:59:06 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-02-28 13:43:45 +0000
commit67a489fdb058acfeda6e453ef145d8ac4cdc5971 (patch)
treeb1bd819f4f3b66f1d0ab09799615b36d8ee2a3e9 /src/soc/intel/cannonlake
parenta198c9d732e1eedd801952108823a5a94ede2839 (diff)
downloadcoreboot-67a489fdb058acfeda6e453ef145d8ac4cdc5971.tar.xz
soc/intel/cannonlake: Disable ACPI mode on BS_DEV_INIT exit
Change ac8c60e (soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init) moved disabling of ACPI mode to pmc_soc_init to keep it more aligned with the behavior on other Intel SoCs. However, as the PMC device is hidden, it never gets enumerated and so init function does not get called for it. This change moves the call to disable ACPI mode to exit of BS_DEV_INIT instead. BUG=b:126016602 TEST=Verified that: 1. pmc_set_acpi_mode is actually getting called. 2. EC panic event gets logged to eventlog correctly. Change-Id: Ie7025e322fa0abc21367a520184a4c7741eba1e6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31633 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/pmc.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 24ddfee796..84bfba06c0 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -158,20 +158,26 @@ static void pmc_init(void *unused)
*/
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
-void pmc_soc_init(struct device *dev)
+static void soc_acpi_mode_init(void *unused)
{
/*
* PMC initialization happens earlier for this SoC because FSP-Silicon
* init hides PMC from PCI bus. However, pmc_set_acpi_mode, which
* disables ACPI mode doesn't need to happen that early and can be
- * delayed till typical pmc_soc_init callback. This ensures that ACPI
- * mode disabling happens the same way for all SoCs and hence the
- * ordering of events is the same.
+ * delayed till typical BS_DEV_INIT. This ensures that ACPI mode
+ * disabling happens the same way for all SoCs and hence the ordering of
+ * events is the same.
*
* This is important to ensure that the ordering does not break the
* assumptions of any other drivers (e.g. ChromeEC) which could be
* taking different actions based on disabling of ACPI (e.g. flushing of
* all EC hostevent bits).
+ *
+ * P.S.: This cannot be done as part of pmc_soc_init as PMC device is
+ * hidden and hence the PMC driver never gets enumerated and so init is
+ * not called for it.
*/
pmc_set_acpi_mode();
}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_acpi_mode_init, NULL);