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| author | Nico Huber <nico.huber@secunet.com> | 2019-06-28 16:12:47 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-07-13 12:47:48 +0000 |
| commit | 8417485f95b07aa76d81d7006fa5097d018d6df2 (patch) | |
| tree | 7c01f6e45a2ec6cf07c7a3b30c2499ef85487dba /src/soc/intel/cannonlake | |
| parent | 0c4ed4bd7edf3c0a131af717eb6dc8aeec44b47e (diff) | |
| download | coreboot-8417485f95b07aa76d81d7006fa5097d018d6df2.tar.xz | |
soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP
We got rid of the dangerous reconfiguration of arbitrary pads in
coreboot, but FSP still overrode that. Make sure that it doesn't
enable a UART for debug output when it isn't configured in core-
boot.
This, again, shows how dangerous it is to leave any FSP UPD at
its binary default.
Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a58a97c060..2367045bdb 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -285,6 +285,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set Debug serial port */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; +#if !CONFIG(SOC_INTEL_COMETLAKE) + params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE; +#endif /* Enable CNVi Wifi if enabled in device tree */ dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); |