summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2020-03-03 20:31:58 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-07 20:32:46 +0000
commitc96f802f7f126dadc41c95a8b63e9dec85cbbfde (patch)
treef01cd58f95e71b7c89bb9a1dfe5279b8d926e0e7 /src/soc/intel/cannonlake
parent7f9ceef51be785781ea4c0035c31d718d590a2fb (diff)
downloadcoreboot-c96f802f7f126dadc41c95a8b63e9dec85cbbfde.tar.xz
intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers
Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/include/soc/smbus.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h
index 54d0d6cfbf..60d155783e 100644
--- a/src/soc/intel/cannonlake/include/soc/smbus.h
+++ b/src/soc/intel/cannonlake/include/soc/smbus.h
@@ -24,9 +24,14 @@
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0A
+#define TCO_INTRD_SEL_MASK (3 << 1)
+#define TCO_INTRD_SEL_SMI (1 << 2)
+#define TCO_INTRD_SEL_INT (1 << 1)
/*
* Default slave address value for PCH. This value is set to match default