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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-07 12:14:33 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-09 15:49:53 +0000 |
| commit | 809aeeed98104c016a5ee1cdd5009a84a5611d8e (patch) | |
| tree | cba013b306c1e18d219f79db9b0c77799fd832b0 /src/soc/intel/cannonlake | |
| parent | 6de6571f1c362c43dbfd04c79d1ddedcb953c724 (diff) | |
| download | coreboot-809aeeed98104c016a5ee1cdd5009a84a5611d8e.tar.xz | |
src/soc: Fix typo
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 4704d1cef6..2dc8c2c55e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -156,7 +156,7 @@ struct soc_intel_cannonlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe ouput clocks type to Pcie devices. + /* PCIe output clocks type to Pcie devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; |