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author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:24:54 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-24 17:05:06 +0200 |
commit | 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 (patch) | |
tree | 7be11b3d97f09f9f5fd176b275d0df3a9c2692e4 /src/soc/intel/common/Kconfig | |
parent | 4a8c19cc90464ad215395bd116c9dc95fc682cac (diff) | |
download | coreboot-0946ec37aa4660ecf16d66cb1174a68df0afc4f0.tar.xz |
Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.
BRANCH=none
BUG=None
TEST=Build for Braswell
Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/Kconfig')
-rw-r--r-- | src/soc/intel/common/Kconfig | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8b5cef354e..7b88d55044 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -3,30 +3,92 @@ config SOC_INTEL_COMMON help common code for Intel SOCs +if SOC_INTEL_COMMON + if HAVE_MRC config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n + help + If CONFIG_USE_FMAP is enabled, it is assumed that a flashmap + containing an RW_MRC_CACHE entry that specifies the location and size + of the cache will be added to the image and present at runtime. if CACHE_MRC_SETTINGS config MRC_SETTINGS_CACHE_BASE hex + depends on !USE_FMAP default 0xffb00000 config MRC_SETTINGS_CACHE_SIZE hex + depends on !USE_FMAP default 0x10000 config MRC_SETTINGS_PROTECT bool "Enable protection on MRC settings" + depends on !USE_FMAP default n endif # CACHE_MRC_SETTINGS endif # HAVE_MRC +config CHIPSET_RESERVED_MEM_BYTES + hex "Size in bytes of chipset reserved memory area" + default 0 + help + If insufficient documentation is available to determine the size of + the chipset reserved memory area by walking the chipset registers, + the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account + for the missing pieces of memory. The value specified in bytes is: + + value = TSEG base - top of low usable memory - (any sizes determined + by reading chipset registers) + +config DISPLAY_MTRRS + bool "MTRRs: Display the MTRR settings + default n + +config DISPLAY_SMM_MEMORY_MAP + bool "SMM: Display the SMM memory map" + default n + +config FSP_CACHE_SIZE + hex "FSP Cache Size in bytes" + default 0 + help + Size of the region in SMM used to cache the FSP binary. This region + size value is used to split the SMM_RESERVED_SIZE config value + into a region specifically for FSP. The remaining region is for + ramstage. + +config SOC_INTEL_COMMON_FSP_RAM_INIT + bool "FSP: Use the common raminit.c module" + default n + depends on PLATFORM_USES_FSP1_1 + +config SOC_INTEL_COMMON_FSP_ROMSTAGE + bool + default n + config SOC_INTEL_COMMON_RESET bool default n + +config SOC_INTEL_COMMON_STACK + bool + default n + +config SOC_INTEL_COMMON_STAGE_CACHE + bool + default n + +config ROMSTAGE_RAM_STACK_SIZE + hex "Size of the romstage RAM stack in bytes" + default 0x5000 + depends on SOC_INTEL_COMMON_STACK + +endif # SOC_INTEL_COMMON |