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| author | Subrata Banik <subrata.banik@intel.com> | 2018-04-19 10:23:30 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-21 15:54:48 +0000 |
| commit | 90d3b2b0c0d63d58d75cf28616724a41e7951e58 (patch) | |
| tree | 50f7801d99fef91f7597af9655f5348647fd75fb /src/soc/intel/common/Kconfig | |
| parent | 2e464cf3b0a475bde87babb27361342708bd00a0 (diff) | |
| download | coreboot-90d3b2b0c0d63d58d75cf28616724a41e7951e58.tar.xz | |
soc/intel/common: Make infrastructure ready for Intel common stage files
Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.
BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.
Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/Kconfig')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 3613965fbf..ea6f10e1f6 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -11,6 +11,9 @@ source "src/soc/intel/common/block/Kconfig" comment "Intel SoC Common PCH Code" source "src/soc/intel/common/pch/Kconfig" +comment "Intel SoC Common coreboot stages" +source "src/soc/intel/common/basecode/Kconfig" + config DISPLAY_MTRRS bool "MTRRs: Display the MTRR settings" default n |