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authorLee Leahy <leroy.p.leahy@intel.com>2016-07-24 08:03:37 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-07-27 13:50:11 +0200
commitae738acdc5f02d232e035538c67d63ba19b9ccaa (patch)
tree862a877545dad919c698b48381a115bd15130fcc /src/soc/intel/common/Kconfig
parent7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b (diff)
downloadcoreboot-ae738acdc5f02d232e035538c67d63ba19b9ccaa.tar.xz
cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions. In this case use a SOC specific routine to support the setting of the MTRRs. Migrate the code from FSP 1.1 to be x86 CPU common. Since all rdmsr/wrmsr accesses are being converted, fix the build failure for quark in lib/reg_script.c. Move the soc_msr_x routines and their depencies from romstage/mtrr.c to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15839 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/Kconfig')
-rw-r--r--src/soc/intel/common/Kconfig7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 776004b1d6..a32252edd8 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -56,13 +56,6 @@ config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
No default is set here as this is an SOC-specific value and must
be provided by the SOC when it selects this driver.
-config SOC_SETS_MTRRS
- bool
- default n
- help
- The SoC needs uses different access methods for reading and writing
- the MTRRs. Use SoC specific routines to handle the MTRR access.
-
config MMA
bool "enable MMA (Memory Margin Analysis) support"
default n