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authorDuncan Laurie <dlaurie@chromium.org>2015-09-08 16:09:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-17 14:13:37 +0000
commit63ebc80e987c6778d5f15583e59a1476d4943c66 (patch)
tree71adb2d211e3b150f5e26b12697c825945fec62f /src/soc/intel/common/Makefile.inc
parentae570d5cee7c8a416ad3887110f172763513e5a4 (diff)
downloadcoreboot-63ebc80e987c6778d5f15583e59a1476d4943c66.tar.xz
intel/common: Add common code for filling out ACPI _SWS
Add common code for filling out the NVS fields that are used by the ACPI _SWS methods. The SOC must provide a function to fill out the wake source data since the specific data inputs vary by platform. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339 Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11646 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/Makefile.inc')
-rw-r--r--src/soc/intel/common/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 892ae9597d..ade5456bf6 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -16,6 +16,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
# Create and add the MRC cache to the cbfs image
ifneq ($(CONFIG_CHROMEOS),y)