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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-28 13:49:39 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 13:01:37 +0000 |
| commit | 18571389d5f6a3882ad0512ead712233a3a117a6 (patch) | |
| tree | 6257f551a08027e5430ae0dddde8017cc87730ec /src/soc/intel/common/basecode | |
| parent | afb3d7e7ecccdc1fbde66fe08252bd97de4df35d (diff) | |
| download | coreboot-18571389d5f6a3882ad0512ead712233a3a117a6.tar.xz | |
device/dram/ddr3: Rename DDR3 SPD memory types
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.
Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/basecode')
0 files changed, 0 insertions, 0 deletions