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author | Subrata Banik <subrata.banik@intel.com> | 2018-05-17 18:28:26 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-25 10:13:08 +0000 |
commit | 7e8998466f6b0cfa410af94da41b18859d6379f2 (patch) | |
tree | 478fe2a24993025500df34f88b3a38811e27fe42 /src/soc/intel/common/block/cse/Makefile.inc | |
parent | 00b7533629b4b227b182d0edca5ee7275054a03b (diff) | |
download | coreboot-7e8998466f6b0cfa410af94da41b18859d6379f2.tar.xz |
soc/intel/common/block: Move cse common functions into block/cse
This patch cleans soc/intel/{cnl, icl, tgl} by moving common
soc code into common/block/cse.
Supported SoC can select existing HECI_DISABLE_USING_SMM option to
select common cse code block to make heci function disable using
sideband interface during SMM mode at preboot envionment.
BUG=b:78109109
TEST=Able to make HECI disable in SMM mode successfully without any hang
or errors in CNL, ICL and TGL platform.
Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/cse/Makefile.inc')
-rw-r--r-- | src/soc/intel/common/block/cse/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 376f00f715..90f76d59b0 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c |