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author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-05-12 21:05:04 +0530 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-05-17 08:33:00 +0000 |
commit | 99dbca381b10a25dabdeb7dd0a03c1a45449b472 (patch) | |
tree | a6be41d0bf0fac1264734b1581ff3d47c794b5a6 /src/soc/intel/common/block/cse/Makefile.inc | |
parent | 17b48033819976405ce0acd8a8a371f166e576b5 (diff) | |
download | coreboot-99dbca381b10a25dabdeb7dd0a03c1a45449b472.tar.xz |
soc/intel/common: Rename cse_is_hfs3_fw_sku_custom()
Rename cse_is_hfs3_fw_sku_custom() to cse_is_hfs3_fw_sku_lite() and
rename custom_bp.c to cse_lite.c. Also, rename all CSE Custom SKU
references to CSE Lite SKU.
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I20654bc14f0da8d21e31a4183df7a2e34394f34e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/cse/Makefile.inc')
-rw-r--r-- | src/soc/intel/common/block/cse/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 418b7a2efa..30ff66bf6f 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,5 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c -ramstage-$(CONFIG_SOC_INTEL_CSE_CUSTOM_SKU) += custom_bp.c +ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c |