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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-06-26 14:29:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-07 08:30:35 +0000 |
| commit | 33aa115574ef70c3ae5baf1a2e489a9a7573052e (patch) | |
| tree | e374b29a3c2847870b74019e33cfb5bbbf13bea0 /src/soc/intel/common/block/cse | |
| parent | b0586d99116fff6f65aa69f8f12eff526f78cdbf (diff) | |
| download | coreboot-33aa115574ef70c3ae5baf1a2e489a9a7573052e.tar.xz | |
soc/intel/common: Log CSE FW Status Registers before triggering recovery
The patch logs CSE Firmware Status Registers(FWSTS1, FWSTS2 & FWSTS3)
before triggering recovery to help debugging.
BUG=b:159962240
Test=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I90e9f5897408bfc37a69cf0bb23bff18a146b9e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43537
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index a12f2d0d29..ff489af9b5 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -153,8 +153,17 @@ struct get_bp_info_rsp { struct cse_bp_info bp_info; } __packed; +static void cse_log_status_registers(void) +{ + printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " + "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1), + me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); +} + static void cse_trigger_recovery(uint8_t rec_sub_code) { + /* Log CSE Firmware Status Registers to help debugging */ + cse_log_status_registers(); if (CONFIG(VBOOT)) { struct vb2_context *ctx; ctx = vboot_get_context(); |