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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2017-09-07 12:15:45 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-11 21:26:27 +0000 |
| commit | b051a9f5348abab842748577eaf4f06418df0ba3 (patch) | |
| tree | 139e0c4938baa9b998c107642a45e78c613442b1 /src/soc/intel/common/block/fast_spi | |
| parent | bfabe62a6e5cdd9e29394b12737c5ed9bd080036 (diff) | |
| download | coreboot-b051a9f5348abab842748577eaf4f06418df0ba3.tar.xz | |
soc/intel/skylake: Fix SPI WP disable status check
Use SPI write protect disable bit from BIOS_CONTROL register
to check write protect status.
Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21449
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/fast_spi')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 078e0ae1f1..87cafb976e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -274,3 +274,21 @@ void fast_spi_early_init(uintptr_t spi_base_address) /* Initialize SPI to allow BIOS to write/erase on flash. */ fast_spi_init(); } + +/* Read SPI Write Protect disable status. */ +bool fast_spi_wpd_status(void) +{ + return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) & + SPIBAR_BIOS_CONTROL_WPD; +} + +/* Enable SPI Write Protect. */ +void fast_spi_enable_wp(void) +{ + device_t dev = PCH_DEV_SPI; + uint8_t bios_cntl; + + bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); + bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD; + pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl); +} |