diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-07-18 13:09:12 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-21 18:53:21 +0000 |
| commit | 3820e3ceed02d21900a060b2c70a031c34cae20d (patch) | |
| tree | 4160ea25f657b868fc7fa18732d9b69acea80e58 /src/soc/intel/common/block/include/intelblocks/gpio_defs.h | |
| parent | f357f7e264baf35f98e216ac59abe71770147f40 (diff) | |
| download | coreboot-3820e3ceed02d21900a060b2c70a031c34cae20d.tar.xz | |
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig
Configuration set to disable (2h = Drive '0') for each pad. Since this
setting doesn't matter for the GPO pad, there is no need to change the
default value for such pads. The patch updates PAD_CFG_GPO* macros to
set trig to disable. It also resolves some problems of creating the
PCH/SoC pads configuration based on information from the inteltool
dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
https://www.intel.com/content/dam/www/public/us/en/documents/
datasheets/100-series-chipset-datasheet-vol-2.pdf
[2] https://review.coreboot.org/c/coreboot/+/34337
[3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/gpio_defs.h')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 0a3e11737a..744095207d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -227,25 +227,29 @@ /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) /* General purpose input */ |