diff options
author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-08-17 11:49:27 +0530 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-25 18:06:25 +0000 |
commit | 4f6e341e88e94e81087a1538b3364dcd47641c7f (patch) | |
tree | 31f663abad816df9d4b7d9733d1773d34c78a35d /src/soc/intel/common/block/include/intelblocks | |
parent | 639bf8a4bd977ec6b44ee008cadcffca85ae61e2 (diff) | |
download | coreboot-4f6e341e88e94e81087a1538b3364dcd47641c7f.tar.xz |
soc/intel/common: Add function to DLOCK PR registers
Add a function in FAST_SPI library to discrete lock the PR
registers 0 to 4.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/21063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/fast_spi.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index b399e4d8fa..086143bc5f 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -49,6 +49,11 @@ void fast_spi_set_opcode_menu(void); */ void fast_spi_lock_bar(void); /* + * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the + * FAST_SPI Protected Range (PR) registers. + */ +void fast_spi_pr_dlock(void); +/* * Set FAST_SPIBAR Soft Reset Data Register value. */ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data); |