diff options
| author | Jamie Chen <jamie.chen@intel.com> | 2020-01-15 10:44:38 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 10:54:09 +0000 |
| commit | 1d534981d9fdc069df9eab2a88d1469cc78554f8 (patch) | |
| tree | 2dab9ead39a8de246f1359a06606efa006c815de /src/soc/intel/common/block/include | |
| parent | b4cac8f763fd118ae98ef375bcb30bce6b9fd7c5 (diff) | |
| download | coreboot-1d534981d9fdc069df9eab2a88d1469cc78554f8.tar.xz | |
mainboard/google/puff: update USB configuration
Base on USB SI report to fine tune the strength and correct
some OC pin settings.
BRANCH=none
BUG=b:147206010
TEST=build and test all usb ports function work fine.
Change-Id: Idbee5cdddf3a83f97109214a95e0f9875b3b3f8f
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
0 files changed, 0 insertions, 0 deletions