diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-01-07 23:36:40 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 10:54:25 +0000 |
| commit | e202e6770951f3207278217bd61d030bec271e03 (patch) | |
| tree | 784c9e92826ed77fca0dce7a8649032a3f844455 /src/soc/intel/common/block/include | |
| parent | 1d534981d9fdc069df9eab2a88d1469cc78554f8 (diff) | |
| download | coreboot-e202e6770951f3207278217bd61d030bec271e03.tar.xz | |
soc/intel/common/cse: Add consistent HECI command id/group id naming
Below changes are done:
1. Consistent HECI command/group ID naming.
2. Rename macros to match with Intel ME BIOS Spec.
3. Move command ids, group ids and related macros into cse.h
4. Add description for structure members.
TEST=Build and Boot hatch board.
Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index b4bfe68924..751c01d565 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -19,6 +19,28 @@ #include <stdint.h> +/* MKHI Command groups */ +#define MKHI_GROUP_ID_CBM 0x0 +#define MKHI_GROUP_ID_HMRFPO 0x5 + +/* Global Reset Command ID */ +#define MKHI_CBM_GLOBAL_RESET_REQ 0xb + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 0x2 + +/* HMRFPO Command Ids */ +#define MKHI_HMRFPO_ENABLE 0x1 +#define MKHI_HMRFPO_GET_STATUS 0x3 + +/* ME Current Working States */ +#define ME_HFS1_CWS_NORMAL 0x5 + +/* ME Current Operation Modes */ +#define ME_HFS1_COM_NORMAL 0x0 +#define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 +#define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 + /* HFSTS register offsets in PCI config space */ enum { PCI_ME_HFSTS1 = 0x40, |