soc/intel/common: Update SA bit fields as per EDS

This patch updates system agent related registers bit definitions
as per EDS.

For example:
As per CNL/ICL EDS MCHBAR register base is between bit 16-38
but coreboot programming was not aligned with EDS previously.

CNL EDS doc number: 566216

Also provide provision to program 64bit values as per SA EDS definitions

TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.

Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index c60595835a..a11bf647d2 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -43,13 +43,13 @@ void bootblock_systemagent_early_init(void);
  * Fixed MMIO range
  *   INDEX = Either PCI configuration space registers or MMIO offsets
  *   mapped from REG.
- *   BASE = 32 bit Address.
+ *   BASE = 64 bit Address.
  *   SIZE = base length
  *   DESCRIPTION = Name of the register/offset.
  */
 struct sa_mmio_descriptor {
 	unsigned int index;
-	uintptr_t base;
+	uint64_t base;
 	size_t size;
 	const char *description;
 };