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author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-11-25 01:07:06 -0800 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-12-08 22:56:31 +0000 |
commit | 63afea54f41cb6054d8a3625238424e381a4fada (patch) | |
tree | 1845bc50f96b62c0d3342ab785e4c911df399a18 /src/soc/intel/common/block/include | |
parent | 493937e1d67e734c2ac45f92280f2c2c22a50b85 (diff) | |
download | coreboot-63afea54f41cb6054d8a3625238424e381a4fada.tar.xz |
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose
Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality:
1. Add a helper function dmi_enable_gpmr which takes as input base,
limit and destination ID to configure in general purpose memory range
registers and then set the GPMR registers in the next available
free GMPR and enable the decoding.
2. Add helper function get_available_gpmr which returns available free
GPMR.
3. This helper function can be utilized by the fast SPI driver to
configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/dmi.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h new file mode 100644 index 0000000000..b771b22022 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_DMI_H +#define SOC_INTEL_COMMON_BLOCK_DMI_H + +#include <types.h> + +/* + * Takes base, size and destination ID and configures the GPMR + * for accessing the region. + */ +enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); + +#endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */ |