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| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-02-17 18:18:32 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-28 16:22:17 +0200 |
| commit | fcab4156c8fea9b48a251325a48ba3872b5abb14 (patch) | |
| tree | f78dc22d4dab1841b2b010cbf9e2901184a1354b /src/soc/intel/common/block/itss/Makefile.inc | |
| parent | f39692ee3e6cd63714e9ec1b3a3243636bb5ca1b (diff) | |
| download | coreboot-fcab4156c8fea9b48a251325a48ba3872b5abb14.tar.xz | |
soc/intel/common/block: Add Intel common ITSS code support
Create Intel Common ITSS code. This code currently only contains
the code for Interrupt initialization required in Bootblock phase.
More code will get added up in the subsequent phases.
Change-Id: I133294188eb5d1312caeafcb621fb650a7fab371
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/19125
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/itss/Makefile.inc')
| -rw-r--r-- | src/soc/intel/common/block/itss/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/itss/Makefile.inc b/src/soc/intel/common/block/itss/Makefile.inc new file mode 100644 index 0000000000..bc0e97a2f9 --- /dev/null +++ b/src/soc/intel/common/block/itss/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c |