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author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-29 16:38:38 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-08-04 14:24:49 +0000 |
commit | bbedef9cfaa23356c79b1318da799450f39ca8e7 (patch) | |
tree | 770bcb6b5fec4c07aeb9ad6ec9e9570e4a2dbd09 /src/soc/intel/common/block/pcie | |
parent | 241bd40966e1cdddd05a159746c4ab8dc3438534 (diff) | |
download | coreboot-bbedef9cfaa23356c79b1318da799450f39ca8e7.tar.xz |
soc/intel/common: Add Cannonlake pci ids for common
Add Cannonlake pci device ids for all the merged intel common code. As
of now only have CNL-U and CNL-Y pci ids.
Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
-rw-r--r-- | src/soc/intel/common/block/pcie/pcie.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index dfc92fed27..19133f0b55 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -139,6 +139,22 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, 0 }; |