diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-12-07 14:55:51 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-12-13 10:20:32 +0000 |
| commit | 6bbc91a96468b97a3e19cdba4641d68e2f2a6f98 (patch) | |
| tree | f3f298b6aab6d1fc21cca733981aa609007639b4 /src/soc/intel/common/block/pcie | |
| parent | ffc790bc7fe35a992e81f0cc31433230a79dfb33 (diff) | |
| download | coreboot-6bbc91a96468b97a3e19cdba4641d68e2f2a6f98.tar.xz | |
soc/intel/common/block: Add option to have subsystem_id in common pci driver
This patch ensures all Intel common PCI devices can
have subsystem ID programmed along with PCI resource
enabling (.enable_resources) as part of PCI enumeration
process.
TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI
subsystem ID getting programmed.
Example:
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/590c
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/591e
Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
| -rw-r--r-- | src/soc/intel/common/block/pcie/pcie.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 19133f0b55..7d383fdfaa 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -24,6 +24,8 @@ #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 +/* PCI-E Sub-System ID */ +#define PCIE_SUBSYSTEM_VENDOR_ID 0x94 static void pch_pcie_init(struct device *dev) { @@ -69,8 +71,16 @@ static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset) PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); } +static void pcie_dev_set_subsystem(struct device *dev, + unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_subsystem = pcie_dev_set_subsystem, }; static struct device_operations device_ops = { |