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| author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-09-20 03:49:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-17 12:16:21 +0000 |
| commit | e26c4a461132087930e7137043ab6ada1b4147c7 (patch) | |
| tree | 14ed0f62eb89c5197d0d783991947ac9e5207083 /src/soc/intel/common/block/pcie | |
| parent | da5491a626955480ae07f5cb944d8aff66a172d0 (diff) | |
| download | coreboot-e26c4a461132087930e7137043ab6ada1b4147c7.tar.xz | |
soc/intel/cannonlake: Add new cannon lake PCH-H support
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
| -rw-r--r-- | src/soc/intel/common/block/pcie/pcie.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index c4b266acc1..2ec37e27b7 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -166,6 +166,30 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24, 0 }; |