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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-04-18 10:11:59 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-20 13:03:54 +0000 |
| commit | e56189cfd1d90a2ca13650a9d21ff82cb79ccda8 (patch) | |
| tree | 0da4c1fec6bdb725e4065d4d687364ae5c63104d /src/soc/intel/common/block/pcie | |
| parent | 6fcb9b00c8b7f820bb5ef81a83a24cd656654272 (diff) | |
| download | coreboot-e56189cfd1d90a2ca13650a9d21ff82cb79ccda8.tar.xz | |
pci: Move inline PCI functions to pci_ops.h
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
| -rw-r--r-- | src/soc/intel/common/block/pcie/pcie.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 7d383fdfaa..4cd057d363 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -18,6 +18,7 @@ #include <device/pciexp.h> #include <device/pci_def.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #define CACHE_LINE_SIZE 0x10 /* Latency tolerance reporting, max non-snoop latency value 3.14ms */ |