diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2018-03-08 16:32:43 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-23 09:04:31 +0000 |
| commit | b7fe7a1a8e033706f39c0fded5901f0f1dce7cfb (patch) | |
| tree | 5314407da68c4d247914b49594f39feb940d3ab3 /src/soc/intel/common/block/scs/Kconfig | |
| parent | c72dc05acc12c65614079bd0de25809b80456141 (diff) | |
| download | coreboot-b7fe7a1a8e033706f39c0fded5901f0f1dce7cfb.tar.xz | |
intel/common/block/scs: Add ability to send early CMD0, CMD1
In order to improve boot time with emmc, add ability to send CMD0
and CMD1 early in romstage. This way, by the time system boots to
payload, we are ready to continue with emmc setup and we don't need
to send CMD0 in payload again, and wait for card to reset and be ready.
BUG=b:78106689
TESTS = Boot to OS
Force early_mmc_wake_hw() to return error, recover in payload
Force an error in payload, make sure system can recover/boot
Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/scs/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/scs/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig index 0a402137bc..06ad8e4fa8 100644 --- a/src/soc/intel/common/block/scs/Kconfig +++ b/src/soc/intel/common/block/scs/Kconfig @@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_SCS bool help Intel Processor common storage and communication subsystem support + +config SOC_INTEL_COMMON_EARLY_MMC_WAKE + bool + default n + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC + select SDHCI_CONTROLLER + help + Send CMD1 early in romstage to improve boot time. It requires emmc + DLL tuning parameters to be added to devicetree.cb |