diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-04-19 18:19:14 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-08 17:49:38 +0200 |
| commit | 52f29743b153e89ca38db5d7a207c676c4c70207 (patch) | |
| tree | afb48119cd2a2d8173a9104adc5b131ca41d6f71 /src/soc/intel/common/block/smbus/smbuslib.h | |
| parent | 1f355178d6b05c9ba14c010b4304835801345f6a (diff) | |
| download | coreboot-52f29743b153e89ca38db5d7a207c676c4c70207.tar.xz | |
soc/intel/common/block: Add Intel common SMBus code
Add below code support under intel/common/block:
* SMBus read/write byte APIs
* Common SMBus initialization code
Change-Id: I936143a334c31937d557c6828e5876d35b133567
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/common/block/smbus/smbuslib.h')
| -rw-r--r-- | src/soc/intel/common/block/smbus/smbuslib.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h new file mode 100644 index 0000000000..b5be6ca84e --- /dev/null +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H +#define SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H + +/* SMBus IO Base Address */ +#define SMBUS_IO_BASE 0xefa0 +/* PCI Configuration Space : SMBus */ +#define HOSTC 0x40 +#define HST_EN (1 << 0) +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 + +#define SMBUS_TIMEOUT 15 /* 15ms */ + +int smbus_read8(unsigned int smbus_base, unsigned int device, + unsigned int address); +int smbus_write8(unsigned int smbus_base, unsigned int device, + unsigned int address, unsigned int data); + +#endif /* SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H */ |