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| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-04 23:32:41 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-28 16:39:50 +0200 |
| commit | 01ae11b057e4b15e1fde48c7845f7fbf66a4e948 (patch) | |
| tree | b98863dcb2d5afae537e244048d25027b55f3c35 /src/soc/intel/common/block/systemagent/systemagent.c | |
| parent | 2ee54db24603f51738cbebd6d80c120f2b4db76d (diff) | |
| download | coreboot-01ae11b057e4b15e1fde48c7845f7fbf66a4e948.tar.xz | |
soc/intel/common/block: Add Intel common systemagent support
Create common Intel systemagent code.
This code currently contains the SA initialization
required in Bootblock phase, which has the following programming-
* Set PCIEXBAR
* Clear TSEG register
More code will get added up in the subsequent phases.
Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/systemagent/systemagent.c')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c new file mode 100644 index 0000000000..58e2c7e054 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <intelblocks/systemagent.h> +#include <soc/pci_devs.h> + +void bootblock_systemagent_early_init(void) +{ + uint32_t reg; + uint8_t pciexbar_length; + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); + + /* Get PCI Express Region Length */ + switch (CONFIG_SA_PCIEX_LENGTH) { + case 256 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_256MB; + break; + case 128 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_128MB; + break; + case 64 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_64MB; + break; + default: + pciexbar_length = PCIEXBAR_LENGTH_256MB; + } + reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1) + | PCIEXBAR_PCIEXBAREN; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + + /* + * TSEG defines the base of SMM range. BIOS determines the base + * of TSEG memory which must be at or below Graphics base of GTT + * Stolen memory, hence its better to clear TSEG register early + * to avoid power on default non-zero value (if any). + */ + pci_write_config32(SA_DEV_ROOT, TSEG, 0); +} + |