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author | Subrata Banik <subrata.banik@intel.com> | 2017-05-19 14:50:09 +0530 |
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committer | Martin Roth <martinroth@google.com> | 2017-06-09 17:05:49 +0200 |
commit | 7609c654b18b232bd0b45621ebd3921d14db8a39 (patch) | |
tree | ecef80a30af6372f3222422ab323e814e440724b /src/soc/intel/common/block/systemagent/systemagent_early.c | |
parent | 43dcbfd85581de4f173953282a4917c1ee9a5922 (diff) | |
download | coreboot-7609c654b18b232bd0b45621ebd3921d14db8a39.tar.xz |
soc/intel/common/block: Add Intel common systemagent support
Add Intel common systemagent support for romstage and ramstage.
Include soc specific macros need to compile systemagent common code.
Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/systemagent/systemagent_early.c')
-rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent_early.c | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c new file mode 100644 index 0000000000..7cf78e7352 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> +#include "systemagent_def.h" +#include <timer.h> + +#if !ENV_RAMSTAGE +void bootblock_systemagent_early_init(void) +{ + uint32_t reg; + uint8_t pciexbar_length; + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); + + /* Get PCI Express Region Length */ + switch (CONFIG_SA_PCIEX_LENGTH) { + case 256 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_256MB; + break; + case 128 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_128MB; + break; + case 64 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_64MB; + break; + default: + pciexbar_length = PCIEXBAR_LENGTH_256MB; + } + reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1) + | PCIEXBAR_PCIEXBAREN; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + + /* + * TSEG defines the base of SMM range. BIOS determines the base + * of TSEG memory which must be at or below Graphics base of GTT + * Stolen memory, hence its better to clear TSEG register early + * to avoid power on default non-zero value (if any). + */ + pci_write_config32(SA_DEV_ROOT, TSEG, 0); +} +#endif + +void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, + size_t count) +{ + int i; + + for (i = 0; i < count; i++) { + uintptr_t base; + unsigned int index; + + index = fixed_set_resources[i].index; + /* Check if PCI BAR already enabled */ + base = pci_read_config32(SA_DEV_ROOT, index); + + /* If enabled don't program it. */ + if (base & 0x1) + return; + + base = fixed_set_resources[i].base; + + pci_write_config32(SA_DEV_ROOT, index, base | 1); + } +} + +/* + * There are special BARs that actually are programmed in the MCHBAR. These + * Intel special features, but they do consume resources that need to be + * accounted for. + */ +void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, + size_t count) +{ + int i; + + for (i = 0; i < count; i++) { + uintptr_t base; + unsigned int index; + + base = fixed_set_resources[i].base; + index = fixed_set_resources[i].index; + write32((void *)(MCH_BASE_ADDRESS + index), base | 1); + } +} + +void enable_pam_region(void) +{ + /* All read and writes in this region are serviced by DRAM */ + pci_write_config8(SA_DEV_ROOT, PAM0, 0x30); + pci_write_config8(SA_DEV_ROOT, PAM1, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM2, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM3, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM4, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM5, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM6, 0x33); +} + +void enable_bios_reset_cpl(void) +{ + u8 bios_reset_cpl; + + /* + * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); + bios_reset_cpl |= 3; + MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; +} |