diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/common/block/uart | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/block/uart')
| -rw-r--r-- | src/soc/intel/common/block/uart/uart.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7f105d7e17..7f213722de 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -45,7 +45,7 @@ static void uart_lpss_init(uintptr_t baseaddr) CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); } -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) +#if CONFIG(DRIVERS_UART_8250MEM) uintptr_t uart_platform_base(int idx) { /* return Base address for UART console index */ @@ -92,7 +92,7 @@ struct device *uart_get_device(void) * config option is not selected. * By default return NULL in this case to avoid compilation errors. */ - if (!IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) return NULL; int console_index = uart_get_valid_index(); @@ -141,7 +141,7 @@ void uart_bootblock_init(void) uart_common_init(uart_get_device(), UART_BASE(CONFIG_UART_FOR_CONSOLE)); - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + if (!CONFIG(DRIVERS_UART_8250MEM_32)) /* Put UART in byte access mode for 16550 compatibility */ soc_uart_set_legacy_mode(); @@ -156,7 +156,7 @@ static void uart_read_resources(struct device *dev) pci_dev_read_resources(dev); /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE) && + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) && uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ @@ -204,7 +204,7 @@ static bool uart_controller_needs_init(struct device *dev) * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing * controller here. */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) return false; /* If this device does not correspond to debug port, then skip. */ |