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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-07-22 11:44:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:35:12 +0000 |
| commit | 23a60fa65bf2ef0e5a31b026830301d7ce0d10ab (patch) | |
| tree | 7c0d7aaa3192f38be676a80938c0728cd4e4f01e /src/soc/intel/common/block | |
| parent | a83a7db80445469369c769ad252e245d0b8e484f (diff) | |
| download | coreboot-23a60fa65bf2ef0e5a31b026830301d7ce0d10ab.tar.xz | |
src/soc/intel: Add include <types.h>
BIT(x) needs <types.h>.
Change-Id: I674e3e423e06ee869366ebbd7c9d4248a2f3d9d9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0cebe329c0..5b703cfcb4 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -9,7 +9,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> #include <soc/soc_chip.h> -#include <stdint.h> +#include <types.h> /* * Set PERF_CTL MSR (0x199) P_Req with |