soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H

Some of the values used for GPIO_CFG and MISCCFG were not correct,
causing GPEs to not work correctly. This adjusts them according to the
values found in the original ACPI tables for the System76 Gazelle.

Unfortunately, the Intel documentation[1] mentioned below is
also incorrect. I have mentioned this to Intel already. The source
for the Intel CoffeeLake FSP also confirms these new numbers.

This was tested on a System76 Gazelle (gaze14). The EC uses GPP_K3 for
its GPE and GPP_K6 is used for the lid switch GPE. Both function
correctly after applying this change.

[1] Intel Document #572235:
    Intel ® 300 Series Chipset Families
    Platform Controller Hub
    External Design Specification (EDS) - Volume 2 of 2

Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

0 files changed, 0 insertions, 0 deletions