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| author | Morgan Jang <Morgan_Jang@wiwynn.com> | 2020-05-25 12:23:59 +0800 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-07-16 13:07:31 +0000 |
| commit | b29d16fc8a1e15a9a5e7f5b389019b7593d42d02 (patch) | |
| tree | c4b732fc6dd19f0a9b67f48eda158bc22b456572 /src/soc/intel/common/block | |
| parent | b8d0d089b307a8e40f12af82d0191d52f8752b37 (diff) | |
| download | coreboot-b29d16fc8a1e15a9a5e7f5b389019b7593d42d02.tar.xz | |
mb/ocp/deltalake: Config PCH PCIe ports in devicetree
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block')
0 files changed, 0 insertions, 0 deletions