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| author | Youness Alaoui <youness.alaoui@puri.sm> | 2017-06-22 15:43:49 -0400 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-16 00:21:49 +0000 |
| commit | b6b1b237eba2d1b817185a32b8bb3f242f3db2b5 (patch) | |
| tree | 79ba4d7bae41e29215d02556f31d40c09aa2c63b /src/soc/intel/common/block | |
| parent | f57f1310c5d48d6b7b5385f60e6e9c4ea04acb59 (diff) | |
| download | coreboot-b6b1b237eba2d1b817185a32b8bb3f242f3db2b5.tar.xz | |
console/flashconsole: Enable support for postcar
If FSP 2.0 is used, then postcar stage is used and the flashconsole
as well as spi drivers needed to be added.
Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/gspi/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gspi/Makefile.inc b/src/soc/intel/common/block/gspi/Makefile.inc index 85cb18ebb8..2eb13fa347 100644 --- a/src/soc/intel/common/block/gspi/Makefile.inc +++ b/src/soc/intel/common/block/gspi/Makefile.inc @@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c |