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authorMichael Niewöhner <foss@mniewoehner.de>2019-10-28 18:55:14 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-10-30 08:30:16 +0000
commite0ad1fa7c82e0a31ec628dd43cbd915550b04f3d (patch)
tree2506b48bd08df9ba8d90a1719939aabd2d90d796 /src/soc/intel/common/block
parenta1dbcb9332e940c11a8e2d5c142b59185309aec2 (diff)
downloadcoreboot-e0ad1fa7c82e0a31ec628dd43cbd915550b04f3d.tar.xz
soc/intel/common: move common memmap functionality from skl,icl,cnl,apl
This moves common memmap functionality from skl,icl,cnl,apl to the common tree. Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/systemagent/Makefile.inc3
-rw-r--r--src/soc/intel/common/block/systemagent/memmap.c48
2 files changed, 51 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc
index 0c29636a94..7e49ec7291 100644
--- a/src/soc/intel/common/block/systemagent/Makefile.inc
+++ b/src/soc/intel/common/block/systemagent/Makefile.inc
@@ -3,3 +3,6 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
new file mode 100644
index 0000000000..ea22aa6d18
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <intelblocks/systemagent.h>
+#include <stdlib.h>
+
+void smm_region(uintptr_t *start, size_t *size)
+{
+ *start = sa_get_tseg_base();
+ *size = sa_get_tseg_size();
+}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+
+ /*
+ * We need to make sure ramstage will be run cached. At this
+ * point exact location of ramstage in cbmem is not known.
+ * Instruct postcar to cache 16 megs under cbmem top which is
+ * a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ top_of_ram -= 16*MiB;
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(pcf);
+}