diff options
| author | Kane Chen <kane.chen@intel.com> | 2017-10-05 10:17:07 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-12 02:45:41 +0000 |
| commit | f73bc0b2d103705a557142461d19496b59adda81 (patch) | |
| tree | 55c5e9a92db40996ffe1f0305e46a538f4d12d8a /src/soc/intel/common/block | |
| parent | 6754e4ea2008f67c0630fdac976456649a5ac95a (diff) | |
| download | coreboot-f73bc0b2d103705a557142461d19496b59adda81.tar.xz | |
soc/intel/skylake: Enable bus master for sata
The bus master needs to be enabled so that
the busy bit in AHCI PORT_TFDATA will be cleared
by controller when depthcharge tries to wait
for sata to complete spin-up during AHCI init.
Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge.
BUG=b:37639063
BRANCH=none
TEST=verify that the sata timeout is gone in
depthcharge
Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/sata/sata.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 5cacc95ce0..f3006569d3 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -45,6 +45,11 @@ static void sata_final(device_t dev) u32 port_impl, temp; dev = PCH_DEV_SATA; + + /* Set Bus Master */ + temp = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); + /* Read Ports Implemented (GHC_PI) */ port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07; /* Port enable */ |