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authorSubrata Banik <subrata.banik@intel.com>2019-07-04 16:26:58 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-07-06 03:22:31 +0000
commit4f61f56be101d472990d631ab592f328117d5dbc (patch)
treefaa9a7cea94214b1e84617193c5cc661d00f1bd0 /src/soc/intel/common/block
parent65f03b7c42152188fbd5ac13cea05aaeb953df31 (diff)
downloadcoreboot-4f61f56be101d472990d631ab592f328117d5dbc.tar.xz
soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width
As per EDS Sata port implemented register is byte width (bits[3:0]) hence converting required DWORD based read/write to BYTE width read/write. TEST=Able to boot from SATA device on CML hatch. Change-Id: I545b823318bae461137d41a4490117eba7c87330 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/sata/sata.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index 0801cb77c4..7dacc6ed92 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -43,14 +43,14 @@ static void *sata_get_ahci_bar(struct device *dev)
static void sata_final(struct device *dev)
{
void *ahcibar = sata_get_ahci_bar(dev);
- u32 port_impl, temp;
+ u8 port_impl, temp;
/* Set Bus Master */
temp = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
/* Read Ports Implemented (GHC_PI) */
- port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
+ port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT))
port_impl = ~port_impl;
@@ -58,9 +58,9 @@ static void sata_final(struct device *dev)
port_impl &= 0x07; /* bit 0-2 */
/* Port enable */
- temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS);
+ temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS);
temp |= port_impl;
- pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp);
+ pci_write_config8(dev, SATA_PCI_CFG_PORT_CTL_STS, temp);
}
static struct device_operations sata_ops = {