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authorMichael Niewöhner <foss@mniewoehner.de>2019-09-22 21:56:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-31 10:35:52 +0000
commit5ce66da1b5ad873cbaa694c850f8816074837e02 (patch)
treef3b9040dad2695186102683f4f42b5fc6915c0dd /src/soc/intel/common/block
parentaf1cbe2278b4ca3252d48ba36814db940e9d4237 (diff)
downloadcoreboot-5ce66da1b5ad873cbaa694c850f8816074837e02.tar.xz
soc/intel/common: add common function to set LT_LOCK_MEMORY
Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which locks most of the chipset BAR registers in accordance to Intel BWG. Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c7
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h3
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h2
3 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 75e71120e0..71e4dbf01b 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -23,10 +23,10 @@
#include <arch/cpu.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/msr.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/pm.h>
-#include <intelblocks/msr.h>
#include <soc/pci_devs.h>
#include <stdint.h>
@@ -320,3 +320,8 @@ void mca_configure(void)
(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
}
}
+
+void cpu_lt_lock_memory(void *unused)
+{
+ msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 8630fd1eb5..1aa88e156d 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -161,4 +161,7 @@ uint32_t cpu_get_max_turbo_ratio(void);
/* Configure Machine Check Architecture support */
void mca_configure(void);
+/* Lock chipset memory registers to protect SMM */
+void cpu_lt_lock_memory(void *unused);
+
#endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 6fdf26e202..3e67fd779d 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -67,6 +67,8 @@
#define MSR_POWER_CTL 0x1fc
#define POWER_CTL_C1E_MASK (1 << 1)
#define MSR_EVICT_CTL 0x2e0
+#define MSR_LT_CONTROL 0x2e7
+#define LT_CONTROL_LOCK_BIT (0)
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301
#define SMM_FEATURE_CONTROL_MSR 0x4e0