summaryrefslogtreecommitdiff
path: root/src/soc/intel/common/block
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-21 18:35:37 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-01 01:54:08 +0000
commitdf128a55b183d3d7a6d7ae986f33abffac50f371 (patch)
tree66f2cef1c9f2516da2783cb945b99f8223e74046 /src/soc/intel/common/block
parenta84a7340b6291e209db2d5a3a28507816eec2223 (diff)
downloadcoreboot-df128a55b183d3d7a6d7ae986f33abffac50f371.tar.xz
intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/pcie/pcie.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 94fa63122e..c8ca4f4d87 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -38,7 +38,8 @@ static void pch_pcie_init(struct device *dev)
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
/* disable parity error response, enable ISA */
- pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
+ pci_update_config16(dev, PCI_BRIDGE_CONTROL,
+ ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
if (CONFIG(PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",