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| author | Patrick Georgi <pgeorgi@google.com> | 2019-12-02 11:43:20 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-03 11:24:49 +0000 |
| commit | 08c8cf9586ab9f75ab6d26fc8d80f14bd8087a1b (patch) | |
| tree | e0a29931e20605d3fb6737413f633549d31d4cf2 /src/soc/intel/common/block | |
| parent | 5cdbce80724d47edcfe0374245b4f304f99f6dd0 (diff) | |
| download | coreboot-08c8cf9586ab9f75ab6d26fc8d80f14bd8087a1b.tar.xz | |
soc/intel/common/cse: Update comment for post-CAR global world
Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 99218253ae..011916dd92 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -146,7 +146,7 @@ static uint32_t get_cse_bar(void) static uint32_t read_bar(uint32_t offset) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return read32((void *)(cse.sec_bar + offset)); @@ -154,7 +154,7 @@ static uint32_t read_bar(uint32_t offset) static void write_bar(uint32_t offset, uint32_t val) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return write32((void *)(cse.sec_bar + offset), val); |