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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-16 16:22:52 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 20:11:24 +0000 |
| commit | 6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd (patch) | |
| tree | 54f4bdf90f1e9ecc9b377b084bfb44396ee0693a /src/soc/intel/common/block | |
| parent | c7a3152273ef3179e3ad5f66f53c4a9d2aa39c8e (diff) | |
| download | coreboot-6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd.tar.xz | |
treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 019976ad8c..49284e9489 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -237,7 +237,7 @@ void fast_spi_cache_bios_region(void) /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will * cause memory type conflict when setting memory type to write - * protection, so limit the cached bios region to be no more than 16MB. + * protection, so limit the cached BIOS region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); if (bios_size <= 0) |