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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:24:54 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-24 17:05:06 +0200 |
| commit | 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 (patch) | |
| tree | 7be11b3d97f09f9f5fd176b275d0df3a9c2692e4 /src/soc/intel/common/mrc_cache.c | |
| parent | 4a8c19cc90464ad215395bd116c9dc95fc682cac (diff) | |
| download | coreboot-0946ec37aa4660ecf16d66cb1174a68df0afc4f0.tar.xz | |
Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.
BRANCH=none
BUG=None
TEST=Build for Braswell
Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/mrc_cache.c')
| -rw-r--r-- | src/soc/intel/common/mrc_cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 6783f18fe3..9a066d533f 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -154,7 +154,7 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(®ion, cache); } -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE /* * romstage code @@ -331,4 +331,4 @@ static void update_mrc_cache(void *unused) BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif /* defined(__PRE_RAM__) */ +#endif /* ENV_ROMSTAGE */ |